1. Field of the Invention
The present invention relates to a ROM testing circuit for testing ROMs embedded in microcomputer chips and particularly, for testing such ROMs in the state of being formed on wafers.
2. Description of the Prior Art
FIG. 3 shows a conventional ROM testing circuit. In FIG. 3, microcomputer chips (hereinafter referred to as "chips") 900, 910 and 920 have PADs 902 to 907, 912 to 917, and 922 to 927 formed thereon, respectively. These PADs can be used as terminals for external connection. When these chips are tested in the state of being formed on the wafers, electrically conductive probes are applied to selected PADs to examine the function of the chips.
Specifically, in chip 900, the output side of PAD 902 is connected to ROM 901, and the output side of ROM 901 is connected to PAD 903. PAD 904 is allotted to a relatively high-voltage source; PAD 905 is allotted to a relatively low-voltage source; PAD 906 is allotted to a reset signal; and PAD 907 is allotted to a clock signal.
This also applies to chips 910 and 920.
The manner in which ROM 901 of chip 900 is tested is explained as follows: PAD 904 is connected to a predetermined high-voltage source (hereinafter referred to as "VDD"); PAD 905 is connected to a predetermined low-voltage source (hereinafter referred to as "GND"); and a reset signal is applied to PAD 906. Then, a signal is applied to PAD 902 to render the test-mode circuit embedded in ROM 901 be in a predetermined state. In response to application of a clock signal to PAD 907, the contents of ROM 901 are outputted to be compared with prescribed or expected values. Thus, a decision can be made as to whether or not ROM 901 can work normally.
Likewise, chips 920 and 930 can be tested.
As disclosed in JPA-5-218157, the self-contained test-mode circuit of ROM 901 and the associated PAD 902 in FIG. 3 can be separately disposed in different chips to reduce the size of chip 900 accordingly.
JPA-6-150698 discloses a technique for facilitating the testing of similar memories embedded in an LSI chip. According to the technique, those memory circuits are made to work simultaneously so that their output signals may be compared with each other to make a decision as to whether or not they can work normally.
As for the conventional ROM testing circuit of FIG. 3, it has the following disadvantages.
First, expected values which are used in making a decision as to whether or not the ROM works normally must be stored in the memory of an LSI tester. In order to meet an ever increasing ROM capacity, the LSI tester need to be equipped with an vast capacity of memory.
Secondly, all the chips must be tested with respect to the function of the self-contained ROM, thus requiring much time involved for the required test.
Thirdly, the contents of ROM 901 appear on PAD 903, whereby the security can not be maintained while strict security must be maintained because of the user's program being written in the ROM.
As for JPA-5-218157, a separate test logic section for each chip must be formed on a selected area in the wafer and the area to be cut away must be included in the wafer, thus requiring a significant extra area exclusively allotted to the cutting-and-separating work of such a test logic section from the chip. Therefore, the number of chips per wafer becomes reduced, although the area of each microcomputer chip can be significantly reduced.
The first and second disadvantages explained above with reference to FIG. 3 cannot be solved in JPA-5-218157 publication.
As for JPA-6-150698, the first and second disadvantages are solved. It, however, relates to an LSI chips having a plurality of the memories of the same word and bit formed therein. These memories can be tested by applying the same input signals thereto at the same time, and by comparing output data with each other. Therefore, this solution is not general, or rather, is practicable only for testing such LSI chips that have the same memory embedded therein.
The memories disclosed in JPA-6-150698 are RAMs which are writable and readable in microcomputers. This is essentially different from the present invention in which the contents of the self-contained ROMs of adjacent chips are compared with each other to make a required test on such ROMs. In the JPA-6-150698, ROMs which store user's programs are not supposed to be used, and therefore, it cannot solve the third disadvantage.